Unified Flash

Integration of both benefits of NOR and NAND on to a single die
   Fast Random Access read of NOR level
   Fast Write of NAND level
   No single bit error and No ECC
   XIP program code and Data storage
   Lower cost per density
   No need to change S/W or H/W. Use industry standard common S/W drive.

Superior Cost Competitiveness

Small cell and chip size, even with its 2-Transistor cell structure
   Comparable unit cell size to conventional NOR cells
   Easy to make Multi-bit-cell product by 2-Transistor cell structure :
      Superior architecture for implementing multi-bit cell in both Performance and Reliability, having       much wider operable Vt window than existing technologies
   Very small circuit area due to Low operating voltage/current, Simple write algorithm, Simple       Test scheme and Unique sensing scheme
   Smaller Core circuit size due to reduced decoder, sense amp and segment area

Shortest Test time and Simple Test Flow
   Simple test flow with removal of reference cell initialization, disturb & over erase-related tests,       high voltage trimming and UV bake
   Resultant very short test time of about 1/20 ~ 1/3 level of competitors.

Very high yield and remarkably short yield ramp-up time
   Enabled by inherent robust cell structure and high reliability

Fewer Photo Masking Steps
   Low process cost and short fab period

Fast Write Speed

UniFlash^TM achieves the utmost fast write speed among flash memories
NAND-compatible fast write and erase speed
   Sector erase - Hundreds times faster than NOR
   Chip Erase - Thousands times faster than NOR
   Program speed - Tens times faster
Fast write speed enables remarkably short test time, only a few % of existing NORs

Fast Read Speed and Low Power consumption

Fast Read speed : enabled by high coupling ratio, wide Vt window, Vcc-only sensing without    voltage boosting
Ultra low active power consumption :
   'no Word line boosting' and 'no DC current in sense amp and cell' during read
   Low operating current/voltage during program
   No preprogram during erase

Low Voltage (Vcc) Operability

Enabled by lowest Cell Operating Voltage and Current
Based on 2-Transistor Cell with separated select transistor

Flexible & Efficient Array Architecture

Easy to construct various types of array architecture
Page size down to EEPROM or EEPROM-like small page of 64-Byte

Fast Development and Production

Simple and Stability-enhanced cell structure and operating methodology
Industry-standard Process & Device Technology, well proven by Long time mass production    throughout industry
UniFlash^TM product design can be manufactured using existing NVM process technology, NOR    or NAND, as it is, or by slightly modifying the already setup process technology at target FAB.

Applicable to All NVM Products

Full-range NOR and NAND-type Flash Memory, including unified (NOR + NAND) flash
Stand-alone and Embedded SoC
Flash Memory and EEPROM

Superior Technology & Cell/Chip Size Scale-ability

Easy layout design rule shrink along with the shrink of process technology, for both cell and
   peripheral devices
Easy electrical bias voltage and current shrink, for both cell and peripheral devices
Based on the Unique cell technology of UniFlash^TM empowered by higher cell design margin

   Lowest Cell Operating Voltage and Current
   Remarkably reduced Punchthrough and Snapback

High Reliability

  Remove reliability problem of existing stack-gate and split-gate cells, by 2-Transistor cell
    structure
   Over-erase (Stack-gate) issue removed
   Bit Line Disturb and Bit line Leakage Current issues (Stack-gate) removed
   Drain-Turn-On issue (Stack-gate) removed
   Select Gate-Turn-On Issue (Split-gate) removed
   Composite Tunnel & Gate Dielectric issues (Split-gate) removed
   Gate Oxide Discontinuity issue (Split-gate) removed